Subcontract Proposal (Summary)

Title of Research and Development Project:
Advanced Parallelizing Compiler Technology
Research theme:
Development of Technologies for the Evaluation of Parallelizing Compiler Performance

1. Applicant

The University of Electro-Communications

2. Contact Information

Hiroki Honda
Postgraduate Research Institute of Information System Studies
TEL 0424-43-5641
FAX 0424-43-8923
e-mail honda@acm.org

3. Details and Objectives of Research and Development

(1) Overview of research and development

Under the theme of " development of technologies for the evaluation of parallelizing compiler performance," this project will establish technologies that provide impartial evaluation of the performance of APC systems, such as the automatic multigrain parallelizing technology that performs parallel processing in SMP systems. Specifically, a format that uses benchmarks to evaluate performance on actual systems will be adopted, so benchmark programs, run rules and evaluation indices will be selected to ensure fair and objective performance evaluation. Because APC technology involves the integration of fairly independent individual functions, individual functions will be evaluated by developing benchmarks from kernels and compact applications, while general performance evaluation will be provided by development of benchmarks from full-scale applications.

(2) Details and objectives of research and development

This project will conduct research and development in benchmarks for evaluation of the performance of APC systems such as the automatic multigrain parallelizing compilers used in SMP systems. This effort consists of 1) preparation and selection of benchmark programs, 2) setting of run rules and 3) setting of measurement indices. The final targets are as follows.

(a) Development of methods for evaluation of individual functions

To evaluate individual functions of parallelizing compilers (testing for presence of functions and the capabilities of individual functions), kernel benchmark programs are prepared, or parts are selected from existing benchmark programs and applications as compact application programs. Indices such as code scalability indices and performance portability indices are taken into consideration.

(b) Development of methods for evaluation of general performance

Existing benchmark programs and application programs are selected as full-scale application benchmark programs for use in evaluating general parallelizing compiler performance, taking code scalability indices and performance portability indices into consideration.

4. Research and Development Track Record

The Honda Laboratory is established in the Parallel Processing Course in the Department of Information Processing Systems Research, The University of Electro-Communications. This laboratory has pioneered important research in parallel processing configuration methods, parallel running methods and automatic parallelizing compiler systems. Over the past three years, the Laboratory has published four papers. In the course of these efforts, the Laboratory has conducted extensive performance evaluation using the systems developed and is thus eminently qualified to carry out the development of technologies for the evaluation of parallelizing compiler performance.

5. R&D System

6. Research and Development Plan

7. FY 2000 Plan (first year)

(1) Details of R&D

A survey will be conducted of the various benchmarks currently diverted for the evaluation of performance in individual functions of parallelizing compilers. Through this survey, guidelines will be clarified for 1) selection of kernel and compact-application benchmark programs, 2) setting of run rules and 3) setting of measurement indices in evaluating the performance of individual functions of parallelizing compilers. Also, guidelines will be clarified for 1) selection of compact-application and full-scale-application benchmark programs, 2) setting of run rules and 3) setting of measurement indices in evaluating the general performance of parallelizing compilers. Finally, a survey will be conducted of the individual functions of existing parallelizing compilers to clarify the current state of the technology.

Subcontract Proposal (Summary)

Title of Research and Development Project:
Advanced Parallelizing Compiler
R&D theme:
Development of Technologies for the Evaluation of Parallelizing Compiler Performance

1. Applicant

Tokyo Institute of Technology

2. Contact Information

Aida Kento
Postgraduate Research Institute, Comprehensive Laboratory of Science and Engineering
Concentrated in Intelligence System Science
TEL 045-924-5168
FAX 045-924-5165
e-mail aida@dis.titech.ac.jp

3. Details and Objectives of Research and Development

(1) Overview of research and development

Under the research theme of " development of technologies for the evaluation of parallelizing compiler performance," this project aims to establish technologies for the evaluation of parallelizing compiler performance, to support the development of parallelizing compiler technology. The project will do this by researching evaluation methods for parallelizing compiler performance and developing suites of benchmark programs for use in the development of this technology.

(2) Details and objectives of research and development

The purpose of this research is to establish performance evaluation methods that will strongly support research and development in parallelizing compilers. Two distinct approaches are taken: Methods to evaluate individual parallelization technologies run in the parallelizing compiler are developed, along with methods using uniform evaluation measures for parallelizing compilers. In the former case, a survey will be conducted of parallelizing technologies run in both research-level and commercial compilers developed hitherto, and a suite developed of benchmark programs that can evaluate the performance of individual technologies. In the latter case, application programs used in the field of scientific and engineering calculation will be collected and surveyed and a suite of benchmark programs developed for overall evaluation of performance among compilers.
The final targets of this R&D project are as follows.

• To develop a suite of benchmark programs for evaluating the performance of individual parallelizing technologies. These programs must be capable of evaluating the performance of each parallelization (optimization) technology used in the parallelizing compiler.
• To develop a suite of benchmark programs for evaluating the general performance of parallelizing technologies. These programs must be capable of evaluating general performance among parallelizing compilers, such as loop parallelizing and multigrain parallelizing compilers, using uniform evaluation measures.

4. Research and Development Track Record

Since 1992 I, Kento Aida, have been pursuing research in parallelizing compilers, particularly in the evaluation of parallelizing performance in coarse-grain-level parallel processing, one of the main parallelizing technologies used in multigrain parallel processing. In addition, I have been actively involved in research on methods of performance evaluation for parallel and distributed processing technologies. In the field of performance evaluation for parallelizing compilers, I have published one academic paper, one international conference paper and one general lecture paper. My research results in automatic multigrain parallelizing compilers include four papers, here international conference papers and 16 general lecture papers.

5. R&D System

6. Research and Development Plan

7. FY 2000 Plan (first year)

(1) Details of R&D

In 2000, a survey is conducted of parallelizing technologies and scientific and engineering calculation applications needed for the development of performance evaluation technologies for individual technologies and for the development of general performance evaluation technologies. In parallel with this survey, work will begin on the development of related benchmark programs. In the survey of parallelizing technologies, relevant academic literature will be surveyed and parallelizing technologies will be surveyed and classified by running programs compiled on existing parallelizing compilers using SMP computers. Work will also begin on examining the development of related benchmark programs. In the survey of scientific and engineering application programs, he scientific and engineering calculation application programs collected by running on parallelizing computers are collected, and parallels are analyzed in terms of loop parallelization and coarse-grain parallelization.

Subcontract Proposal (Summary)

Title of Research and Development Project: Advanced Parallelizing Compiler
R&D theme: Development of APC Technology

1. Applicant

The Toho University

2. Contact

Department of science
Name: Yoshida Akimasa
TEL (047) 472-8201
FAX (047) 470-0966
e-mail yoshida@is.sci.toho-u.ac.jp

3. Details and Objectives of Research and Development

(1) Overview of research and development

In this project, automatic data distribution technology is developed as part of the automatic multigrain parallelizing technology used in the development of APC technology. To achieve high effective performance in multigrain parallel processing, as many parallels as possible must be extracted from tasks in multiple grains from throughout the entire program, and data transfer between processors must be minimized. This project develops automatic data distribution technology to send data between tasks through local memory.

(2) Details and objectives of research and development

This project proposes an automatic data distribution format to minimize data transfers between processors by drawing a large number of task parallels from the program, resulting in high effective performance in multigrain parallel processing.
This project develops an automatic data distribution method that conducts data transfer between coarse-grain tasks, which are connected to each other through a data-dependent edge, through local memory on the processor, rather than through central shared memory. This technique will achieve high effective performance in multigrain parallel processing tasks. The procedure for R&D consists of developing methods of coarse-grain task distribution that distribute data and processing so that data definitions and reference range are applied equally in sets of coarse-grain tasks where data transfer is frequent. In multiple coarse-grain tasks so distributed, a timing/scheduling method is developed to assign data and processing to processors at the time of processing to enable data to be received through local memory.
The novelty of this approach is that, whereas automatic data distribution technology used in conventional dynamic scheduling environments was applied only to a specified loop set, this approach will enable data to be received through local memory between coarse grains over a wide scope within the program, significantly reducing data transfer overhead.
The final target of this project is to use the automatic data distribution technology developed herein to achieve a performance improvement of 30% or more in one or more of the evaluation programs selected in the final year of the project, in comparison with cases where this technology is not used.

4. Research and Development Track Record

I, Akimasa Yoshida, have long been active in research in automatic data distribution (data localization) for automatic parallelizing compilers. My work has been published in six academic journals and at five international conferences. These accomplishments underscore my excellent qualifications as a participant in the development of automatic data distribution technology.

5. R&D System

6. Research and Development Plan

7. FY 2000 Plan (first year)

(1) Details of R&D

In FY 2000, automatic data distribution technology will be developed to conduct data transfer between coarse-grain tasks through local memory, rather than through shared memory. This innovation will expand the range of application of data transfer through local memory from conventional partial programs to entire programs, reducing data transfer overhead.
This project will develop in FY 2000 an automatic data distribution method that conducts data transfer between coarse-grain tasks, which are connected to each other through a data-dependent edge, through local memory on the processor, rather than through central shared memory. This technique will achieve high effective performance in multigrain parallel processing tasks. First, a method will be developed to determine the range of application of data reception through local memory, considering parallels in coarse-grain tasks throughout the program. Next, methods of coarse-grain task distribution are developed that distribute data and processing so that data definitions and reference range are applied equally in domains that are candidates for receipt of data through local memory (coarse-grain task sets). Finally, a timing/scheduling method is developed to assign data and processing to processors at the time of processing to enable data to be received through local memory. The novelty of this approach is that, whereas automatic data distribution technology used in conventional dynamic scheduling environments was applied only to a specified loop set, this approach will enable data to be received through local memory between coarse grains over a wide scope within the program.