About APC

3 Research and Development Implementation Structure

1. Research Organization and Management System

1-1. Officers in Charge of Research Implementation

Responsible for research implementation:	Takashi Ichikawa, Managing Director, Department Administrator of Technology Planning Department, JIPDEC
Accounting Manager:	Akira Tanaka, Comprehensive Accounting Auditor, Administrative Department, JIPDEC

1-2. Organization Chart

1-3. Research Locations

Key Laboratories

1. Waseda University, faculty of science and engineering
3-4-1, Okubo, Shinjuku-ku, Tokyo

**Equipment used in research and development**
Equipment type	Details
Fujitsu VX (university equipment)	Supercomputer (performance: 8.8Gflops)
Main-memory shared-multiprocessor server	Hitachi SR4300 multiprocessor system SMP system connecting eight IBM PowerPC processors. Capable of running a subset of OpenMP, the system will be used for auxiliary performance evaluation in coarse-grain parallel processing that uses a small number of processors.
DSM multiprocessor server	SGI 2100 multiprocessor system Cache-coherent non-uniform memory access (CC-NUMA) machine connecting eight MIPS R10000 processors. OpenMP-compatible, the system will be used for auxiliary performance evaluation of data distribution technology in small-scale systems.
Multiprocessor workstation	Fujitsu GP400S model 80 (SUN Ultra80-level) SMP workstation consisting of four UltraSparc II processors. To be used for research and development in compiler technology and performance evaluation technology.
Workstation	Sun Ultra 60 workstation, etc. To be used for research and development in compiler technology.

Date from which the R&D facilities can be used and floor space available

Date from which the R&D facilities can be used

August 2000

Floor space available 70m²

Associate laboratories

1. Hitachi. Ltd. System Development Laboratory
1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa

Reasons for placement of Associate laboratories

One item of computing equipment that is essential for research and development in APC technology and technologies for the evaluation of parallelizing compiler performance, the SGI Origin2000, requires a specific and demanding operating environment. It requires a dedicated power supply (200V 60A), special climate control equipment (heat capacity of 9,440Kcal/hour) and ample space (18m²). In the main laboratories, obtaining an installation location that satisfies all of these requirements on short notice is physically impossible and beyond the budget of this project. To conduct research and development using this equipment, therefore, existing laboratory facilities are used. All utilities costs (climate control, light and water) for this equipment will be borne by Hitachi. For security reasons, the system can only be used on-site at the system development laboratory above and at two remote locations where remote access will be made available. Project members will only be permitted access to these locations to use this equipment.
Hitachi Ltd. Software Development Department
Kaneichi Building, 549-6 Shinanomachi, Totsuka-ku, Yokohama-shi, Kanagawa

Research and development themes

(1) Research and development in APC technology
(2) Research and development in technologies for the evaluation of parallelizing compiler performance

R&D equipment held by the project

Model

Details

SGI Origin2000

DSM machine consisting of 32 MIPS10000 processors. To be used in development of automatic multigrain parallelizing technology and technologies for the evaluation of parallelizing compiler performance.

HP9000 C360 *2

PA-RISC processor workstation. To be used by researchers for program development.

HP9000 C180 *2

PA-RISC processor workstation. To be used by researchers for program development.

Date from which the R&D facilities can be used and floor space available

Date from which the R&D facilities can be used

June 2000

Floor space available

Laboratory: 52m²
Computing room: 22m²

2. Fujitsu Ltd. 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi 211-8588
140 Motomiya, Numazu-shi, Shizuoka 410-03

Reasons for placement of associate laboratories

The Fujitsu GP7000 Fmode 11000, another item of computing equipment that is essential for research and development in APC technology and technologies for the evaluation of parallelizing compiler performance, also requires a specific and demanding operating environment. Because the CPU configuration must be changed frequently, the location must support the permanent stationing of specialist engineers. Operation of the equipment requires a dedicated power supply (200V 28.5A), special climate control equipment (heat capacity of 20,420J/hour) and sufficient space (3m2). In the main laboratories, obtaining an installation location that satisfies all of these requirements on short notice is physically impossible and beyond the budget of this project. To conduct research and development using this equipment in the Kawasaki area, therefore, the existing laboratory facilities listed above are used.
New equipment must be introduced for use in verification of parallelizing compiler technology. To verify this parallelizing compiler technology, the CPU configuration must be changed frequently. These changes must be performed directly by specialist engineers, who must be permanently stationed at the facilities. In view of the scarcity of engineers with the specialized expertise required, as well as the special space, climate control and power requirements listed above, the equipment must be located in the Numazu area, where these personnel are already stationed.

All utilities costs (climate control, light and water) for this existing research facility will be borne by Fujitsu. Project members will only be permitted access to these locations to use this equipment.

Research and development themes

(1) Research and development in APC technology
(2) Research and development in technologies for the evaluation of parallelizing compiler performance

R&D equipment held by the project

Model

Details

FujitsuGP7000Fmode11000

SMP machine consisting of 16 SPARC processors. To be used in development of automatic multigrain parallelizing technology.

FujitsuS-4/20H *6

SPARC processor workstation. To be used by researchers for program development.

FujitsuS-7/400 *4

SPARC processor workstation. To be used by researchers for program development.

Date from which the R&D facilities can be used and floor space available

Floor space available:

10m² in Kawasaki 20m² in Numazu

Date from which the R&D facilities can be used:

from April 2000

2. Names of Researchers

Name	Location and post	Key research history and achievements
Sumio Kikuchi	Manager, Planning Office Systems Development Laboratory Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	17 years' experience in compiler research and development, including automatic vector/parallelization and scalar optimization. From FY 1997 to 1999, worked in research and development of parallelizing platform technology at RWCP. 15 patents pending (four in the United States), 10 dissertations and theses.
Takayoshi Iizuka	Unit leader and chief researcher Unit 305, Department 3 Systems Development Laboratory Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Employed with the company 17 years, working in research and development of optimization and parallelization technology related to supercomputers and massively parallel processors. From FY 1997 to 1999, worked in research on interprocedural parallelization technology at RWCP. Exhibited and announced results of R&D efforts at Supercomputing '99. Nine patents pending (four in the United States), 5 dissertations and theses (one dissertation overseas).
Makoto Sato	Chief researcher Unit 305, Department 3 Systems Development Laboratory Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Employed with the company 13 years, working in research and development of optimization, parallelization and tuning support technology related to supercomputers and massively parallel processors. From FY 1997 to 1999, worked in research on interprocedural parallelization technology and technology for visualization of parallelization status at RWCP. Exhibited and announced results of R&D efforts at Supercomputing '99. 10 patents pending (two in the United States), 10 dissertations and theses (two dissertations overseas).
Hiroshi Ohta	Chief researcher Unit 305, Department 3 Systems Development Laboratory Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of parallelization technology and automatic data distribution technology related to massively parallel processors for 10 years, since his third year with the company. From FY 1997 to 1999, worked in research and development of automatic data distribution technology for distributed memory systems at RWCP. 18 patents pending (one in the United States), 13 dissertations and theses (three dissertations overseas).
Takashi Hirooka	Researcher Unit 305, Department 3 Systems Development Laboratory Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of parallelization technology and automatic data distribution technology related to massively parallel processors for 11 years, since his fifth year with the company. From FY 1997 to 1999, worked in research and development of automatic data distribution technology for DSM systems at RWCP. 7 patents pending (1 in the United States), 2 dissertations and theses.
Yuichiro Aoki	Researcher Unit 305, Department 3 Systems Development Laboratory Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Worked in research and development of parallelization technology for supercomputers and massively parallel processors for six years, since his first year with the company. From FY 1997 to 1999, worked in research in interprocedural parallelization and task parallelization technology at RWCP. Exhibited and announced results of R&D efforts at Supercomputing '99. Four patents pending, three dissertations and theses.
Kiyomi Wada	Researcher Unit 305, Department 3 Systems Development Laboratory Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of parallelization technology for supercomputers and massively parallel processors for nine years, since his first year with the company. From FY 1997 to 1999, worked in research and development of interprocedural parallelization and optimization code generation technology at RWCP. Exhibited and announced results of R&D efforts at Supercomputing '99. Four patents pending, one dissertation/thesis.
Tadayasu Takabatake (Doctor of Engineering)	Researcher Unit 305, Department 3 Systems Development Laboratory Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Before joining the company, worked in research and development of program parallelization technology as a professor at Denki Tsushin University. 11 dissertations and theses (one dissertation overseas).
Eiji Nunohiro (Doctor of Engineering)	Chief engineer Language Department Software Development Division Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of optimization and parallelization technology for supercomputers and massively parallel processors as well as numerical calculation technology and development support for 15 years, since his first year with the company. From FY 1997 to 1999, worked in research in automatic data distribution technology for distributed memory systems at RWCP. 15 patents pending (two in the United States), 15 dissertations and theses.
Ichiro Honma	Engineer and unit leader Language Department Software Development Division Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of optimization and analytical technology for supercomputers and massively parallel processors for 17 years, since his first year with the company. From FY 1997 to 1999, worked in research in automatic data distribution technology for distributed memory systems at RWCP. Two patents pending, two dissertations and theses.
Yasuhito Nishiya	Language Department Software Development Division Hitachi, Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of parallelization technology and automatic data distribution technology for supercomputers and massively parallel processors for six years, since his first year with the company. From FY 1997 to 1999, worked in research in automatic data distribution technology for distributed memory systems at RWCP. Three patents pending, seven dissertations and theses.
Yasunori Kimura (Doctor of Engineering)	Assistant department manager No. 1 Computer Department Computer Division Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research in computer architecture and compilers for 15 years, since his first year with the company. From FY 1997 to 1999, worked in research in parallelization platform technologies at RWCP. 52 patents pending, 17 dissertations and theses.
Koichiro Horita	Manager Compiler Technology Department Middleware Division Software Group Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of automatic vectorization, parallelization and optimization of compilers for 20 years, since his first year with the company. 45 patents pending five dissertations and theses.
Eiji Yamanaka	Compiler Technology Department Middleware Division Software Group Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of automatic vectorization, parallelization and distributed parallel languages for 12 years, since his first year with the company. From FY 1997 to 1999, worked in research and development of distributed multiprocessor parallelization technology at RWCP. Exhibited and announced results of R&D efforts at Supercomputing '99. 13 patents pending, 1 dissertation/thesis.
Kiyofumi Suzuki	Compiler Technology Department Middleware Division Software Group Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of automatic vectorization and parallelization of compilers for 13 years, since his first year with the company. 14 patents pending, 1 dissertation/thesis.
Masanori Kaneko	Compiler Technology Department Middleware Division Software Group Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of compiler parallelization and distributed parallel languages for seven years, since his first year with the company. From FY 1997 to 1999, worked in research and development of distributed multiprocessor parallelization technologies at RWCP. Exhibited and announced results of R&D efforts at Supercomputing '99. One patent pending.
Masatoshi Haraguchi	Compiler Technology Department Middleware Division Software Group Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of compiler optimization for seven years, since his first year with the company. Five patents pending one dissertation/thesis.
Toshihiro Ozawa	Assistant department manager No. 1 Computer Operations Development Department Computer Division Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research in language processing, suppression of memory delay in compilers and instruction parallels for 15 years, since his first year with the company. From FY 1997 to 1999, worked in research in parallelizing platform technologies at RWCP. Exhibited and announced results of R&D efforts at Supercomputing '99. 58 patents pending, four dissertations and theses.
Akira Anzai	Assistant department manager No. 1 Computer Operations Development Department Computer Division Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research in processor architecture and speculative running for 12 years, since his first year with the company. From FY 1997 to 1999, worked in research in parallelizing platform technology at RWCP. 74 patents pending, 1 dissertation/thesis.
Satoshi Hosoi	No. 1 Computer Operations Development Department Computer Division Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of language processing, processor architecture and instruction parallelization in compilers for 10 years, since his first year with the company. From FY 1997 to 1999, worked in research and development of parallelizing platform technologies at RWCP. 20 patents pending, 1 dissertation/thesis.
Masaki Arai	No. 1 Computer Operations Development Department Computer Division Fujitsu Ltd. Concurrently serves as an officer of JIPDEC	Has been working in research and development of language processing, processor architecture and instruction parallelization in compilers for eight years, since his first year with the company. From FY 1997 to 1999, worked in research and development of parallelizing platform technologies at RWCP. Four patents pending.

3. Subcontracted Research

Part of this research and development work is subcontracted to certain universities. This section provides a list of subcontractors and a list of the research items subcontracted to each, along with detailed information about the intended subcontractors and the reasons for their selection. For each intended subcontractor, a proposal is attached. In addition to the subcontracted research, joint research was conducted with the Electrotechnical Laboratory to achieve speculative running using dynamic data.

3-1. The University of Electro-Communications

Work in speculative running technology in technologies for the evaluation of parallelizing compiler performance (1), "Development of methods to evaluate performance of individual functions" and (2), "Development of methods to evaluate general performance," was subcontracted to the Honda Laboratory of the Parallel Processing Course, Information Networks Program, School of Information Systems, Denki Tsushin University. The reasons for subcontracting this research to this facility are that (1) it is desirable to entrust research and development in evaluation methods to a research facility not affiliated with a particular company, given the nature of this research, and (2) it is desirable to entrust this research and development to a university with a broad base of academic and technical knowledge of this field.
The Honda Laboratory has conducted a great deal of pioneering research and development work in the field of parallel processing, including configuration methods for parallel computers, parallel running methods and automatic parallelizing compilers. These results have been published by a number of academic societies, as the list below indicates. In the course of this research work, this laboratory has also conducted performance evaluation with respect to the systems it developed, demonstrating excellent proficiency in the development of technologies for the evaluation of parallelizing compiler performance."

1) "A One-to-one Synchronous Configuration for Fine-grain Parallel Processing in Multiprocessor Systems," (Hayakawa, Honda), Journal of the Information Processing Society, Vol. 38, No. 8, pp1630-1637,1997

2) "Proposal and Performance Evaluation for an RCBQ Synchronous Configuration and Related Synchronous Method," (Hayakawa, Honda), Journal of the Information Processing Society, Vol. 39, No. 6, pp1655-1663,1998

3) "Performance Measurements on Sandglass-type Parallelization of Doacross Loops (Takabatake, Honda, Osawa, Yuba), Journal of the Information Processing Society

3-3. Tokyo Institute of Technology, Vol. 40, No.5, pp2037-2044, 1990

4) Performance Measurements on Sandglass-Type parrallelization of Doacross Loops (M.Takabatake, H.Honda, T.Yuba), Proc. Of 7^th Int. Conf. High-Performance Computing and Networking (Lecture Notes in computer Science 1993, Springer), pp663-672, 1999.

3-2. Tokyo Institute of Technology

Work in technologies for the evaluation of parallelizing compiler performance (1), "Development of methods to evaluate performance of individual functions" and (2), "Development of methods to evaluate general performance," was subcontracted to the Aida Laboratory at Tokyo Industrial University. To carry out this research and development project, R&D work is required from researchers with a thorough knowledge of technologies for the evaluation of parallelizing compiler technology and parallel processing technology. The Aida Laboratory has been involved in parallelizing compiler research since 1992, particularly in the field of evaluation of performance in coarse-grain-level parallel processing, a key technology involved in multigrain parallel processing. In addition, since 1997 the Aida Laboratory has been conducting research on methods of performance evaluation for parallel and distributed processing technologies. For these reasons excellent results are expected in subcontracting this R&D work to the Aida Laboratory.

3-3. The Toho University

Work in automatic data distribution technology in APC technology (1), "Development of automatic multigrain parallelizing technology," was subcontracted to the Yoshida Laboratory of the Department of Information Sciences, Faculty of Science, The Toho University. This facility conducts research in automatic data distribution technologies for parallelizing compilers. In 1996 Prof. Akimasa Yoshida, director of the Yoshida Laboratory, earned the title of Professor of Engineering at Waseda University for his work on data localization in automatic parallelizing compilers. The Yoshida Laboratory continues to perform R&D work in automatic data distribution technology and has published its results in the form of six academic theses and five presentations at international conferences. These points indicate that Prof. NAME Yoshida of Toho University is an excellent choice for subcontracting of research on automatic data distribution technology.