Advanced Parallelizing Compiler Technology
Basic Plan for Research and Development in Industrial Science

1. Objectives, Details and Targets of Research and Development

(1) Objectives of research and development

Large-scale, high-speed numerical analysis by computers supports a poad range of industries, forming an integral part of plant systems in energy development, the automobile industry, power generation and steelmaking. This important technology is widely expected to play a key role in the development of the revolutionary products and exciting new markets of the future. As high-performance computers (HPCs) are developed to fulfill the need for high processing power, the strengthening of high-speed data processing through smarter software will emerge as an issue of crucial importance.
In recent years the HPC market has seen the debut of mid-range servers in which several microprocessors are connected in parallel. Presently technologies to accelerate microprocessors have begun to approach hard limits, motivating a shift from single-processor to multi-processor systems. These multi-processor machines are expected to penetrate a poad range of industries, forming core technology underpinning much of modern business and social activity.
At the present time, however, the parallelizing compilers required by multi-processor systems are written in a special programming language that is abstruse, difficult to use and inadequate for boosting hardware performance to its full potential. In fact, this software tends to drag down effective performance (the ratio of actual performance in running applications to the theoretical speed of the processor).
In light of this situation, today's industries urgently await the development of a parallelizing compiler technology that makes multi-processor computer systems easy to use and delivers higher effective performance.
This research and development project therefore adopts a radical departure from existing parallelizing compiler technologies. Writing code in a more versatile and user-friendly language, the project team eschews compiler technologies based on existing parallelization. Rather than merely distributing program tasks to specified processing grains, this project is conducting research and development of platform-free automatic parallelizing compiler (APC) technology in which the compiler automatically allocates scheduling of programming grains to the optimum processing unit. Through these efforts, the project team intends to improve ease of use and double effective performance in the multi-processor computer systems of future PCs, workstations and HPCs.
The potential applications for this technology are numerous and far-reaching. APC technology will build and expand the market for next-generation PCs, workstations and HPCs and lead to the creation of exciting new industries. In turn, these computers will be used in many fields of enterprise to create the products of the future. Furthermore, APC will support EC in Japan and bolster the competitive position of the nationﾕs financial industry, which needs to process vast amounts of data (information) rapidly.
A priority of this project will be to develop an open technological platform that can be used across a poad swath of industries.

(2) Details and targets

This R&D project in APC technology includes research and development into the following items, based on the R&D plan attached separately.

1. Development of APC technology
2. Development of technology to evaluate the performance of parallelizing compilers

In addition, the following technologies will be developed to form an open platform for APC technology.

1. Establishment and organization of basic philosophies, principles and concepts, and methods for achievement of same
   • Automatic multigrain parallelizing technology
   • Parallelizing tuning technology
2. Provision of testing and evaluation methods and tools
   • Technologies for evaluating the performance of parallelizing compilers
3. Proposal and adoption of standards (including de facto standards)
   • Establishment of an expanded version of the parallelizing description language

2. Format for Implementing Research and Development

(1) Implementation framework

The project team is committed to promoting a research and development program that maximizes the R&D potential of each group participating in this joint project, whether from the private sector, government or academia. With that perspective, a centralized management framework is adopted, in which members from each of these three sectors are gathered together under the authority of the manager of the each R&D facility to conduct focused and far-reaching research and development activities.
This research project is the result of a joint research contract concluded among national laboratories nominated by the Agency of Industrial and Science Technology(AIST) and private-sector companies nominated by the New Energy and Industrial Technology Development Organization (NEDO), including research bodies at universities that carry out research subcontracted from original contractors (herein called "subcontractors").
To ensure a cohesive approach to R&D, NEDO is forming close links with both the R&D managers and the Industrial Technology Council. NEDO uses this framework to gather data on the state of progress by the R&D managers and ensure that the project is run appropriately.

(2) Establishment of a Promotion Committee

To stimulate the progress of the research and development project, a Promotion Committee was established within NEDO, consisting of NEDO, R&D managers and other distinguished persons required to ensure the smooth operation of the project.

3. Period of Implementation of R&D

The period of implementation of the R&D project is a three-year period from 2000 to 2002.

4. Other Important Items

(1) Evaluation of R&D

After the R&D project is complete, the significance and achievements of the project will be evaluated from a technological and industrial-policy perspective, and the results will be evaluated for both their technological significance and potential influence on future industry.

(2) Handling of R&D results

Publication of R&D papers
The results of the R&D project will be published prominently both in Japan and overseas.

Connection to construction of a knowledge base and standardization
To link the results of the project to the creation of a knowledge base and the process of standardization, all data gathered will be organized in database form and standard reports (TR:Technical Reports) issued.

Handling of intellectual property rights
The intellectual property rights affecting the results of the R&D carried out under contract from NEDO are as stipulated in Article 9 of the NEDO Industrial Technology R&D Manual. In principle, all rights are solely the possession of the contractors.

(3) Changes to the basic plan

To ensure that the details of the R&D program remain appropriate, the project team members will from time to time review the details of the basic plan as necessary from both a technological and an industrial-policy point of view. Such reviews will consider trends in R&D both in Japan and overseas and the status of R&D costs.

---

(Appendix) R&D Plan

R&D Item 1: Development of Advanced Parallelizing Compiler Technology

1. The Need for Research and Development

Conventional parallelizing compiler technologies merely find parallels among single grains of programs. In the coming generation of mid-range servers and HPC systems, however, hardware configurations will shift from multiple processors on a single chip to concatenations of large numbers of such chips. Given the versatility and complexity of such systems, this single grain parallelization paradigm will be unable to provide sufficient effective performance. A revolutionary new, automatic parallelizing technology is needed that can be applied to a wide range of such hardware.
Such hardware requires the development of an automatic "multigrain" parallelizing technology that elicits phased mutual parallelization among the "fine grain"(the instruction level), the "medium grain" (array processing level) and the "coarse grain" (supoutines and basic blocks). This radically new approach will improve the effective performance of multiprocessor computer systems and provide unprecedented convenience to users, who previously required sophisticated knowledge of parallel processing to use such technology.

2. Specific Details of R&D

(1) Development of multigrain parallelizing technology

The purpose of this project is to develop a platform-free automatic parallelizing compiler (APC) whose input is in a source program written in a general sequential programming language such as Fortran or C and whose output is in an expanded parallelizing description language.
An automatic multigrain parallelizing technology will be developed in which each part of the program is allocated to a grain in a phased and appropriate manner, to extract parallels automatically in each phase for effective parallel processing. This technology will include data-sensitive analytical technology, speculative execution technology, automatic data distribution technology and scheduling technology.
Standard programming languages will be used in the expanded parallelizing description language (such as the expanded version of OpenMP) used for output.

(2) Development of parallelizing tuning technology

The project team will develop an interactive, platform-free parallelizing tuning tool. This tool will accelerate processing using active information unavailable to the static analysis conducted by compilers, such as profile data that indicates panching probability and other behavior of programs.

3. Targets

(1)	The project team aims to establish a platform-free, automatic multigrain parallelizing technology that can automatically extract parallels from each level of a program to conduct highly effective parallel processing.
(2)	The project team aims to establish an interactive parallelizing tuning technology that uses profile data gleaned from active analysis.
(3)	To evaluate the technology developed in (2) above, the project team aims to run the expanded parallelizing description language used for output on an actual multiprocessor computer system, such as will serve as the actual platform for this technology. In so doing, the team will use the evaluation method specified in "development of a technology for evaluating the performance of the parallelizing compiler" in [2] to double the performance of the compiler. It will do this by comparing the performance of the automatic parallelizing compiler in multiple, differing shared-memory multiprocessor (SMP) systems as it extracts parallels in existing single grains.

R&D Item [2]: Development of a technology for evaluating the performance of the parallelizing compiler

1. The Need for Research and Development

The performance of computer systems is generally evaluated using benchmarks such as SPEC. These benchmarks are normally developed to evaluate the performance of hardware, however, and so cannot really be used as a fair test of the performance of parallelizing compiler technology. Some benchmarks, such as the SWIM program of the SPEC CPU95fp benchmark, can achieve almost peak performance in the hardware for single-grain parallelizing compilers, while others, such as the FPPPP program of the SPEC CPU95fp benchmark, are unable to boost performance because of the restrictions of the hardware, no matter how much the parallelizing compiler is optimized.
Existing benchmarks used to evaluate hardware and computer systems are therefore inadequate to measure the performance of APC. The project needs an impartial technology for evaluating the contribution of compiler technology to the improvement of multiprocessor computer systems.

2. Specific Details of Research and Development

The following technologies will be developed for the evaluation of advanced parallelizing technologies such as the automatic multigrain parallelizing technology developed in [1] Development of Advanced Parallelizing Compiler Technology, for use in SMP systems.

(1) Methods for evaluation of individual functions

The project team will conduct R&D into methods to evaluate the performance of individual functions in the compiler. Specific individual technologies that these methods will evaluate include automatic multigrain parallelizing technology, data-sensitive analytical technology, speculative execution technology, automatic data distribution technology and scheduling technology.

(2) Methods for general performance evaluation

The project team will conduct R&D into methods for evaluating the general performance of the parallelizing compiler technology that is independent of the hardware configuration and the performance of the hardware. A benchmark program will be written for general-evaluation purposes (including components selected from existing benchmarks and applications) and methods developed for evaluating the general performance of parallelizing technology.

3. Target

By using these methods for evaluation of the systems developed in [1] Development of Advanced Parallelizing Compiler Technology, the project will establish a technology for the objective evaluation of the performance of parallelizing compilers for SMP systems.