 |
Outline
The purpose of this project is to develop the platform-free automatic parallelizing compiler technology that extracts multi-grain parallelism hierarchically from a whole program. It dramatically improves the usability and the cost-performance of multiprocessor systems that have been widely used in HPC (High Performance Computing).
The research and development is to be carried out in accordance with the following themes.
|
(1) |
Development of Advanced Parallelizing Compiler Technology |
| (2) |
Development of Performance Evaluation Technology for Parallelizing Compiler |
The research and development allows us to double the effective performance, or the essential performance when applications run, and significantly improve the usability of multiprocessor systems that will be a primary architecture in next-generation PC (personal computer), WS (workstation), and HPC.
Advanced Parallelizing Compiler Technology
This R&D project for the development of an advanced parallelizing compiler (APC) technology is the Millennium Project of the Ministry of Economy, Trade and Industry, a joint public-private research and development effort. Based on the Industrial Science and Technology Research and Development System (ISTRDS), a system for nurturing new industries, a body was created under the auspices of the Industrial Technology General Development Framework to conduct R&D in advanced parallelizing compiler technology beginning September 2000. Headed by Project Leader (PL) Dr. Hironori Kasahara, Special Professor at the Faculty of Science and Engineering of Waseda University, the body consists of the Japan Information Processing Development Corporation, a team of 21 researchers from Hitachi, Ltd. and Fujitsu Ltd. nominated by JIPDEC, two collaborating research organizations (National Institute of Advanced Industrial Science and Technology(AIST) and Waseda University) and subcontractors The University of Electro-Communications, Tokyo Institute of Technology, and The Toho University.
This project will develop software that boosts the cost-performance of multi-processor systems (computers that organically link multiple CPUs to deliver high computing performance), also called high-performance computing (HPC) systems, and makes them easy to use. To achieve this objective, the project aims to establish platform-free, automatic parallelizing software that can elicit phased parallelization of multiple elements from a single program. Given the intense competition in the field of high-performance computing R&D, the project team aims to complete its work within a mere three years. Also, for the first time the ISTRDS will adopt a "networked intensive laboratory method" format, linking the participating research organizations online to maximize the effectiveness of the projectﾕs computing resources and bolster R&D efficiency. To provide an international assessment and advisory framework, prominent European researchers will lend their talents to an Advisory Committee.
The purpose of the APC project is to enhance the ease of use of high-performance multi-processor systems installed in PCs, workstations (WSs) and HPCs, and to double the actual performance, called the effective performance, of applications that use them. These systems are based on the single-chip multiprocessor, which is expected to dominate the next generation of microprocessor architectures. Through the development of APC, the project team expects to reduce the cost of processing by half without replacing the hardware. In carrying out this profound improvement in cost-performance and ease of use, the project team seeks to buttress the competitive strength of the Japanese computer industry and provide the basic research that will underpin the nationﾕs competitiveness in fields that require high-speed computing capability, such as environmental studies, gene analysis, pharmaceuticals, financial engineering, automobile design and aerospace development.
